Altera Corporation · San Francisco
Otherposted 4w ago
About Altera
At Altera™, our independence as the world’s largest pure‑play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry‑leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely—empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.
About the Role
We are seeking a seasoned and technically deep Sr. Director of Silicon Hardware Engineering (Boards, Packages, and Reliability) to lead a global, distributed organization spanning chip package development, board development, and silicon power and reliability engineering. Reporting directly to the VP of Engineering, this leader will be accountable for defining and executing hardware development strategies that deliver world-class silicon solutions at scale. The ideal candidate combines hands-on technical expertise in advanced semiconductor technologies with a proven track record of operational excellence, cross-functional collaboration, and team leadership across US and Asia sites.
Team & Organizational Leadership
Lead and grow three core engineering functions: chip package development, board development, and silicon power and reliability.
Build, mentor, and develop high-performing engineering teams distributed across US and Asia, fostering a collaborative, results-driven culture.
Partner closely with VP/SVP leadership to define multi-year roadmaps, headcount plans, and organizational strategy.
Establish clear goals, KPIs, and performance expectations across all teams.
Technical Excellence
Drive technical decision-making for advanced package technologies including 2.5D/3D IC, flip-chip, and high-density interconnect.
Oversee board-level hardware development from concept through bring-up, ensuring design-for-manufacturability and design-for-test.
Champion rigorous signal integrity (SI) and power integrity (PI) methodologies, ensuring adoption of best-in-class EDA tooling across teams.
Lead silicon power and reliability programs including power budgeting, electromigration, ESD, and reliability qualification.
Apply deep knowledge of silicon design development methodologies to improve tapeout quality, schedule, and first-pass silicon success rates.
Operations & Vendor Management
Own end-to-end program execution across multiple concurrent programs, driving on-time and on-budget delivery.
Develop and execute cost reduction strategies across packaging, board materials, and test processes without compromising quality.
Manage complex, multi-vendor relationships with OSATs, PCB fabricators, substrate suppliers, and EDA vendors.
Implement robust supplier qualification, scorecard, and escalation processes to ensure supply chain resilience.
Drive continuous improvement in cycle time and cost through data-driven operational reviews.
Stakeholder Engagement
Serve as the primary engineering interface for internal customers including silicon architecture, SoC design, system integration, and product management teams.
Represent hardware engineering in executive reviews, customer engagements, and technology partnership discussions.
Communicate complex technical tradeoffs clearly to non-technical stakeholders and senior leadership.
Salary Range
The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.
$231,500 - $335,000 USD
We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.
Minimum Qualifications:
B.S. in Electrical Engineering, Computer Engineering, or closely related field required; M.S. preferred.
15+ years of progressive experience in semiconductor hardware engineering, with at least 5 years in a senior leadership or director-level role.
Demonstrated experience managing global, cross-functional engineering teams across US and Asian sites (e.g., Taiwan, South Korea, Japan).
Deep technical expertise in chip package development (advanced packaging, substrate design, OSAT management).
Proven experience in chip board hardware development including schematic, layout, and bring-up.
Strong hands-on background in signal integrity and power integrity analysis tools (e.g., Ansys SIwave, Cadence Sigrity, HyperLynx).
Solid understanding of silicon design development methodologies, including synthesis, P&R, timing closure, and DFT.
Track record of delivering measurable cost reduction programs across package and board hardware.
Experience managing and qualifying multiple external vendors and OSATs simultaneously.
Excellent communication and executive presentation skills.