Altera · San Francisco
Other
About Altera
At Altera™, our independence as the world’s largest pure‑play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry‑leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely—empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.
About the Role
Altera is seeking a Silicon Domain Architect to support the definition and development of next-generation FPGA silicon architecture. This role will contribute to the architecture and technology direction of silicon domain subsystems, with a focus on security technologies, Root of Trust (RoT), FPGA configuration capabilities, and hardware/software integration.
The ideal candidate will have experience in semiconductor architecture, silicon design, and hardware security concepts, with the ability to translate system requirements into architectural specifications and collaborate with cross-functional engineering teams. This role will work closely with hardware design, firmware, software, validation, and product teams to help define and deliver scalable silicon solutions throughout the product lifecycle.
The Silicon Domain Architect will contribute to future FPGA product generations by supporting subsystem architecture development, evaluating technology solutions, and helping drive implementation of secure, high-performance, and power-efficient silicon features.
Key Responsibilities
Develops and contributes to end-to-end architecture definitions for silicon domain subsystems, including Root of Trust (RoT) and FPGA configuration-related features within Altera FPGA products.
Supports the definition and execution of technology roadmaps for silicon domain subsystems based on product requirements, hardware features, and hardware/software interoperability needs.
Contributes to the development and evaluation of innovative technologies for domain subsystems, including security architectures, Root of Trust, FPGA configuration features, and related silicon capabilities.
Works with architecture and engineering teams to define microarchitectural features and specifications for future FPGA products targeting high performance, security, scalability, and low-power requirements.
Translates system-level requirements into silicon architecture specifications, technical requirements, and implementation guidelines.
Defines and documents architectural requirements, interfaces, and design considerations for complex silicon subsystems.
Develops test plans, validation strategies, and testing infrastructure requirements for new architectures and silicon features.
Performs functional modeling, simulations, and architecture analysis to evaluate design tradeoffs, benchmark performance, and identify optimization opportunities.
Applies knowledge of security technologies to Root of Trust and FPGA configuration blocks, translating security requirements into architectural solutions for silicon platforms.
Collaborates with cross-functional teams, including hardware design, firmware, software drivers, validation, and product engineering teams, to define hardware/software integration and configuration control requirements.
Supports architecture reviews, technical discussions, and resolution of complex silicon design challenges throughout the product development lifecycle.
Salary Range
The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.
$118,900 - $178,000 USD
We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.
Minimum Qualifications
Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field
At least 4 years of experience in one or more of the following areas:
Development of semiconductor architecture, silicon design, SoC architecture, FPGA architecture, or related hardware engineering disciplines.
Defining or contributing to hardware architectures, microarchitectures, or semiconductor subsystems.
Hardware security technologies, including secure boot, RoT concepts, cryptographic foundations, trusted computing technologies, or security-focused silicon features.
Translating system requirements into hardware architecture specifications, technical requirements, or design documentation.
Collaborating with hardware, firmware, software, validation, or product engineering teams to support semiconductor product development.
Defining or analyzing hardware/software interfaces, firmware interactions, configuration requirements, or system integration considerations.
Performing architectural analysis, evaluating design tradeoffs, and optimizing semiconductor designs for performance, power, security, or scalability.
Preferred Qualifications
Master’s degree or Ph.D. in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
At least 5 years of experience in one or more of the following areas:
Experience with semiconductor architecture, SoC design, FPGA architecture, or silicon development.
Experience developing security architectures, Root of Trust implementations, secure lifecycle management capabilities, or FPGA security features.
Experience with FPGA, ASIC, SoC, CPU subsystem, or other complex semiconductor architectures.
Experience developing architectural models, simulation environments, benchmarking methodologies, or performance analysis techniques.
Previous work on FPGA configuration flows, secure provisioning, device authentication, cryptographic acceleration, or platform security technologies.
Previous work across hardware and software teams to define system-level solutions and resolve technical challenges.