Altera · San Francisco
Other
Altera is seeking a technically strong Transceivers & Protocol IP Application Engineer to be based in San Jose California Altera Office to help customers and partners successfully adopt Altera FPGA transceiver and protocol IP solutions. This role serves as a trusted technical advisor across the customer design cycle—from architecture and IP selection through implementation, hardware bring-up, validation, optimization, and production readiness.
The engineer will work closely with regional application engineering, sales, silicon design, IP development, software, validation, documentation, and product teams. The role combines hands-on FPGA design and debug with customer communication, technical leadership, and product improvement.
Provide expert technical guidance on Altera high-speed transceiver PHYs and protocol IP, including architecture, IP configuration, clocking, reset, PLL/CDR behavior, channel placement, link bring-up, and system integration.
Support customer designs using protocols such as Ethernet, PCIe, JESD204B/JESD204C, CPRI/eCPRI, Interlaken, DisplayPort, HDMI, SerialLite, and PMA/FEC Direct PHY configurations, as applicable to the assigned product portfolio.
Review customer system architectures, schematics, constraints, RTL, IP parameterization, simulation results, timing reports, and hardware measurements; identify risks and recommend practical corrective actions.
Reproduce and isolate customer issues using Quartus Prime, design examples, System Console, Signal Tap, Transceiver Toolkit, simulation environments, development kits, and laboratory equipment.
Diagnose problems spanning FPGA IP, transceiver configuration, firmware, reference clocks, signal integrity, resets, data paths, protocol behavior, Quartus flows, and customer application logic.
Own technical cases from initial analysis through resolution, maintaining clear problem statements, evidence, investigation plans, customer updates, and closure documentation.
Collaborate with engineering teams to escalate suspected product, IP, silicon, software, or documentation defects with sufficient reproduction data and technical analysis.
Drive issue resolution and corrective actions, including improvements to design examples, user guides, application notes, knowledge-base content, tools, and customer workflows.
Provide technical training, workshops, design reviews, demonstrations, and hands-on enablement for customers, partners, sales teams, field application engineers, and internal engineering teams.
Participate in product pre-enablement and release readiness activities; evaluate new devices, transceiver features, protocol IP releases, and customer use cases before broad deployment.
Communicate customer feedback and recurring technical issues into product definition, usability, validation, documentation, and future IP requirements.
Develop scripts, test collateral, reference designs, and automation in Python, Tcl, Bash, or similar languages to improve debug efficiency and customer adoption.
Contribute to a globally coordinated support model by sharing expertise, consulting with peers, and mentoring engineers in transceiver and protocol-IP domains.
Salary Range
The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.
$149.1K - $215.9K USD
We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.
Required Qualifications
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical discipline.
Professional experience in FPGA applications, high-speed digital design, ASIC/FPGA validation, protocol IP development, field application engineering, or technical customer support.
Hands-on experience with FPGA design flows and hardware debugging using Quartus Prime or a comparable FPGA development environment.
Working knowledge of high-speed serial interfaces, transceiver PHY concepts, clocking, PLLs, CDRs, resets, equalization, link training, channel bonding, and signal-integrity fundamentals.
Experience reading and debugging RTL, IP configuration files, timing constraints, simulation waveforms, register maps, and hardware logs.
Proficiency in at least one hardware description language, such as Verilog, SystemVerilog, or VHDL.
Scripting or software-development experience in Python, Tcl, Bash, C, or C++.
Strong analytical, problem-solving, prioritization, and technical writing skills.
Ability to communicate clearly with customers and cross-functional engineering teams, including when the root cause is still under investigation.
Ability to manage multiple technical issues and priorities while maintaining ownership, responsiveness, and high-quality records.
Preferred Qualifications
Experience with Altera Agilex, Stratix, Arria, or Cyclone FPGA families and associated transceiver tiles or PHY architectures.
Knowledge of Ethernet MAC/PCS/FEC, PCIe, JESD204, CPRI/eCPRI, Interlaken, DisplayPort, HDMI, or other high-speed protocol IP.
Experience with Quartus Prime Pro, Platform Designer, System Console, Signal Tap, Transceiver Toolkit, ModelSim, Questa, or similar EDA and debug tools.
Experience performing board-level bring-up, eye-diagram or BER analysis, loopback testing, protocol analysis, or lab-based transceiver characterization.
Experience creating customer-facing documentation, training material, application notes, reference designs, or design examples.
Experience working with regional application engineering, field application engineering, silicon, IP, software, validation, and technical communications organizations.
Willingness to travel occasionally for customer meetings, workshops, design reviews, or hardware bring-up support.