Architect Labs · San Francisco
Hardware & ElectricalHardwareFullTime
Architect is a frontier AI lab for custom silicon. We partner with frontier labs, clouds / neoclouds, physical AI companies, and advanced fabs to tape-out custom chips co-designed for next-generation AI workloads. Our goal is to compress end-to-end software to silicon timelines, and maximize intelligence per watt and per dollar for the world. We are a small exceptional team across silicon, systems, software and frontier AI. Our team have led research teams at nearly every frontier AI lab, and at some of the most complex SoCs in the world.
As a Founding Member of the Technical Staff on the RTL Design team at Architect, you’ll own the AI-driven microarchitecture and RTL design of high-performance networking subsystems going into production silicon. You will define, drive, and revise the block-level micro-architecture specification for Ethernet MAC engines, packet processing pipelines, and network datapath logic — ensuring line-rate performance, protocol compliance, and seamless SoC integration.
Own the network datapath RTL end-to-end: from IEEE 802.3-compliant MAC engine design through code generation, lint, CDC, synthesis, and timing closure using our AI-driven design flow.
Design and implement Ethernet MAC engines: including 802.3 MAC/PCS layers, FCS generation/checking, flow control (802.3x pause, PFC), auto-negotiation state machines, and rate adaptation logic for multi-speed operation (10G/25G/50G/100G/400G+).
Architect packet processing datapaths: including Tx/Rx FIFO management, packet buffering and scheduling, credit-based flow control, descriptor management, and DMA interfaces for host-to-network data movement.
Work directly with the principal architect to refine microarchitectural specs, resolve implementation trade-offs (latency vs. throughput vs. area), and feed area/timing/power realities back into the architecture and internal AI systems.
Define and maintain interface specifications: MII/GMII/XGMII/CGMII variants, AXI-Stream for packet data, AXI for CSR/DMA, and custom sideband signaling for scheduling and QoS.
Build and maintain RTL infrastructure for our in-house AI-driven flow: design automation scripts, regression flows, lint/CDC waivers, and integration collateral for the networking subsystem.
Close collaboration with DV: Support verification bring-up with protocol-aware reference models, SVA assertions for protocol compliance, coverage plans targeting corner-case packet scenarios, and architectural documentation for verification closure.
Close collaboration with SW and ML: Support and guide our SW and ML experts to revise and improve our in-house AI flow based on your networking domain expertise.
Support FPGA prototyping on Xilinx for early functional validation of the network datapath, including interoperability testing with commercial PHYs and switches.
Degree: Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a closely related field.
Experience: 5+ years (10+ preferred) in RTL design with at least one advanced-node tapeout experience involving networking or packet-processing silicon (NICs, switches, SmartNICs, or networking SoC subsystems).
802.3 Expertise: Deep familiarity with IEEE 802.3 Ethernet standards — MAC sublayer operation, PCS encoding (64b/66b, Reed-Solomon FEC), reconciliation sublayer, and multi-lane distribution/alignment.
MAC Engine Design: Hands-on experience designing or owning Ethernet MAC blocks including Tx/Rx pipelines, inter-packet gap management, preamble/SFD processing, FCS computation, VLAN tagging, and jumbo frame support.
SystemVerilog: Clear, synthesizable, lint-clean RTL with strong design habits — parameterization for multi-rate support, modularity for protocol layering, and configurability for different deployment targets.
Packet Datapath Depth: Hands-on experience with packet buffering architectures, credit-based and descriptor-based DMA engines, store-and-forward vs. cut-through trade-offs, and scheduling/arbitration for network QoS.
SoC Methodology: Solid grasp of synthesis, timing constraints, clock domain crossings (especially between MAC clock domains and core clocks), reset strategies, AMBA protocols (AXI, AXI-Stream), and power management.
Python: Strong skills for design automation, regression infrastructure, protocol compliance test generation, and tooling.
PPA Ownership: Experience taking a networking block from RTL through synthesis and working with PD teams on timing/area/power closure — particularly for high-frequency datapath logic.
Experience with high-speed SerDes integration and PHY-side interfacing (CAUI, 56G/112G PAM4 SerDes).
Familiarity with RDMA, RoCEv2, or TCP offload engine architectures.
Experience with traffic management: scheduling algorithms (WRR, DWRR, strict priority), shaping, and policing.
Low-power design techniques: clock gating for idle ports, power gating for unused lanes, multi-voltage domains.
FPGA prototyping experience (Xilinx Vivado/Vitis), especially with Ethernet hard IPs or soft MAC cores.
SVA assertions for protocol compliance checking (e.g., inter-frame gap, pause quanta timing, alignment marker lock).
Prior IP building and delivery experience for Ethernet MAC/PCS or NIC subsystem blocks.
Domain-specific research contributions: publications or patents in network-on-chip, datacenter networking, or high-performance packet processing hardware.
You’ll join a founding team building the future of chip design at the intersection of AI and silicon. Your networking expertise will directly shape production ASICs and influence how AI transforms hardware development — from spec to tapeout.