Cisco · San Francisco
Otherposted 2w ago
The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms powering Cisco’s core Switching, Routing, and Wireless products. We design networking hardware for enterprises, service providers, the public sector, and nonprofit organizations worldwide. As part of the team behind Cisco Silicon One—the industry’s only unified silicon architecture spanning top-of-rack switches to web-scale data centers—you’ll help shape Cisco’s groundbreaking solutions by designing, developing, and testing some of the most advanced ASICs in the industry.
Lead the end-to-end characterization flow for standard cell libraries from extracted netlists through Liberty delivery and correlation against TSMC reference data.
Define and maintain PrimeLib/Liberate characterization methodology, templates, and automation for timing, power, noise (CCS/NLDM), and leakage across PVT and RC corners.
Drive correlation closure for delay, transition, capacitance, and leakage.
Own extraction-to-char integration: LVS/StarRC setup, RC corner alignment (e.g., cbest_CCbest_T), well-bias port handling (VPP/VBB), and netlist quality gates.
Debug characterization failures at the netlist, simulation, and Liberty-model level; root-cause issues in extraction, corner mismatch, bias connectivity, or SPICE model binding.
Develop reusable Tcl/shell flows, validation checks, and documentation so characterization is repeatable across cells, corners, and library releases.
Partner with library design, physical verification, and CAD teams on cell readiness, deck configuration, and release criteria.
Lead characterization reviews; define sign-off criteria and drive closure on blockers before library release.
Bachelor's degree in Electrical Engineering, Computer Science, or a related field and 6 years of relevant experience, or Master's Degree and 4 years of experience, or PhD and 1 year of experience.
First-hand experience characterizing standard cell libraries with PrimeLib, Liberate, or equivalent tools
Strong understanding of Liberty formats (NLDM, CCS, CCS noise, leakage/power modeling) and TSMC (or equivalent foundry) characterization flows
Experience with parasitic extraction (StarRC or equivalent), LVS, and RC corner / PVT alignment between extraction and characterization
Solid understanding of CMOS device behavior, timing arcs, power domains, and well/substrate bias effects in deep-submicron nodes
Preferred Qualifications
Experience on advanced nodes (7 nm, 5 nm, 3 nm, 2 nm) with foundry std-cell libraries
Familiarity with TSMC N2P (or similar) char packages, SPICE kits, and extraction guides
Experience with LVF/statistical characterization and hold-margin flows
Background in library QA, automated correlation reporting, and release management for high-volume silicon
Proficiency in Tcl, Perl, or Python for flow automation and correlation analysis
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