Micron (San Jose ops) · Boise
Mechanical & Aerospace
Our vision is to transform how the world uses information to enrich life for all.
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
At Micron, we're not just designing chips. We're building the physical architecture that powers artificial intelligence, accelerates cloud computing, enables autonomous vehicles, and connects the world through mobile and edge devices. Every breakthrough in AI — from large language models to next-generation data centers — runs on memory. And every bit of that memory lives inside a package that someone like you designs!
We're looking for a Senior Package Design Engineer who is passionate about sadvanced semiconductor packaging and ready to lead at the intersection of silicon, system, and scale. This is a high-impact, highly visible role where you'll work across the full product lifecycle — from early-stage co-design with silicon teams all the way to High Volume Manufacturing (HVM).
If you thrive where precision meets innovation, where your decisions shape products reaching millions of users worldwide, and where your expertise directly influences how the AI era unfolds — this role is for you!
Responsibilites:
Lead Co-Design from Silicon to System
- Partner with silicon design, Business Units, customers, and package architecture teams to define new product concepts from the earliest stages of chip development
- Optimize die floorplans, interconnection schemes, and package architectures — from concept to HVM
- Drive trade-off studies and architecture decisions for advanced DRAM products targeting AI/Data Center, Mobile, Automotive, and Edge Computing applications
Own Package Layout and Architecture
- Lead floorplanning, high-density routing, placement, and package layout for advanced memory packages
- Define and optimize substrate stack-ups, wire bond and flip chip interconnect schemes, and BEOL/RDL flows
- Create wire bond diagrams, interposer drawings, and complete manufacturing documentation packages
Drive Electrical and Physical Design Quality
- Partner with Signal Integrity (SI) and Power Integrity (PI) teams to incorporate simulation results into design decisions
- Conduct DFM reviews and feasibility studies; interpret parasitic modeling and validation data
- Drive material selection decisions based on simulation, reliability, and manufacturability data
Collaborate Globally to Scale and Sustain
- Partner with OSAT assembly partners, substrate suppliers, and Technology Development teams to define design rules and advance routing methodologies for next-gen solutions
- Lead DFMEA reviews and define assembly DOEs to ensure HVM readiness
- Support continuous improvement: global design alignment, IP development, competitive analysis, and package design roadmaps
Minimum Qualifications
- Bachelor's degree in Electrical Engineering, Mechanical Engineering, Materials Science, or related field + 5 years of semiconductor package design experience
- OR Master's degree in the above fields + 3 years of semiconductor package design experience
- Hands-on proficiency with advanced package EDA tools such as Cadence Allegro Package Designer+, Cadence Integrity 3D-IC, or Siemens/Mentor Xpedition
- Experience with flip chip, wire bond interconnects, BEOL/RDL flows, substrate stack-ups, and high-density routing
- Experience partnering with SI/PI simulation teams to drive package architecture and design optimization
- Experience collaborating with OSAT partners or assembly engineering organizations to deliver designs through HVM
Preferred Qualifications
7 plus years of proven experience with advanced DRAM technologies — LPDDR, HBM, or GDDR
- Experience with TSV stacking, micro-bump layout, and Chip-Package Interaction (CPI) analysis
- Familiarity with 2.5D/3D-IC, Fan-Out Wafer Level Packaging (FOWLP), and System-in-Package (SiP)
- Experience with Assembly DOE definition, DFMEA reviews, and process/material development in HVM
- Proficiency with AutoCAD / Autodesk Mechanical for package and interposer drawings
- Experience leading co-design engagements and silicon floorplan optimization
- Experience and/or interest in developing Agentic AI workflows into current or future processes.
As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits.
Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.
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To learn more about Micron, please visit micron.com/careers
For US Sites Only: To request assistance with the application process and/or for reasonable accommodations, please contact Micron’s People Organization at hrsupport_na@micron.com or 1-800-336-8918 (select option #3)
Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.
Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.
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